Hardware emulators are programmable devices used to verify hardware circuit designs and integrated circuits having very high logic densities, i.e. large numbers of logic gates. A common method of design verification is to use processor-based hardware emulators to emulate the design prior to physically manufacturing the integrated circuit embodying the circuit design. These processor-based emulators sequentially evaluate combinatorial logic levels in the circuit design under verification, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
Hardware emulators allow engineers and hardware designers to test and verify the operation of an integrated circuit, an entire board of integrated circuits, or an entire system without having to first physically fabricate the hardware. The complexity and number of logic gates present on an integrated circuit increases significantly every year. In order to emulate such large, high-gate-count, integrated circuits, processor-based hardware emulators now commonly contain dozens or hundreds of emulation chips, each emulation chip containing hundreds or thousands of processors. The emulation chips must efficiently communicate in the process of emulating the design under verification. The term “emulation chip” is used broadly to include both monolithic integrated circuits as well and multi-chip packages. These emulation chips themselves are generally ASICs, designed or configured specifically for use in emulation.
As emulation systems continue to grow in size and complexity, the bandwidth requirements of the controlling interface grows. The latency requirements of the interface also tighten. In current emulation systems, the various emulation chips and other circuit components of the emulation system are often interconnected in a mesh network of packetized serial links. The emulation chips operate with a synchronous clock, such that the individual emulation chips operate in lockstep with each other, starting and stopping synchronously. The synchronous clock is transmitted from a common point where it is generated, and distributed to each of the emulation chips. The emulation chips can then communicate using that common clock signal. Signals are launched on a clock edge in one chip and captured on some future clock edge in a second chip. The frequency of that clock defines the bandwidth of the interconnect wires, which frequency is limited by the size and accuracy of the clock distribution scheme. In order to synchronize the various chips, such that they can start stepping operations at the same time, a synchronized signal is sent simultaneously to all the emulation chips. The distribution network for this synchronization signal is often complex and limits the signaling frequency. As a result, more efficient means of synchronization are desired.